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dc.contributor.authorHaung, YRen_US
dc.contributor.authorYuang, MCen_US
dc.date.accessioned2019-04-02T06:00:52Z-
dc.date.available2019-04-02T06:00:52Z-
dc.date.issued1996-01-01en_US
dc.identifier.issn1018-4864en_US
dc.identifier.urihttp://dx.doi.org/10.1007/BF02114304en_US
dc.identifier.urihttp://hdl.handle.net/11536/149409-
dc.description.abstractIn this paper, we propose an input access scheme for input-queued ATM multicast switches, achieving high system throughput, low packet delay and packet loss probability. Multicast and unicast packets of each input port are separately queued. Multicast queues take priority over the unicast queues, and both types of queues are fairly served in a cyclic-priority access discipline. In particular, each unicast queue is handled on a window-service basis, and each multicast packet is switched in a one-shot scheduling manner. To evaluate the performance of the access scheme, we propose an approximate analysis based on a simplified cyclic-priority model for an N x N finite-buffer multicast switch possessing Bernoulli multicast and unicast arrivals, with window-service (for unicasting) and one-shot scheduling (for multicasting) both taken into account. Finally, we show simulation results to demonstrate the accuracy of the approximate analysis and the superiority of the scheme over existing schemes with respect to normalized system throughput, mean packet delay, and packet loss probability.en_US
dc.language.isoen_USen_US
dc.titleA high-performance input access scheme for ATM multicast switchingen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/BF02114304en_US
dc.identifier.journalTELECOMMUNICATION SYSTEMSen_US
dc.citation.volume6en_US
dc.citation.spage367en_US
dc.citation.epage379en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:A1996WP98100008en_US
dc.citation.woscount0en_US
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