完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTseng, HCen_US
dc.contributor.authorChang, CYen_US
dc.contributor.authorPan, FMen_US
dc.contributor.authorChen, LPen_US
dc.date.accessioned2019-04-02T05:59:55Z-
dc.date.available2019-04-02T05:59:55Z-
dc.date.issued1997-06-01en_US
dc.identifier.issn0013-4651en_US
dc.identifier.urihttp://dx.doi.org/10.1149/1.1837770en_US
dc.identifier.urihttp://hdl.handle.net/11536/149564-
dc.description.abstractThree isolation oxide structures have been prepared to study their resistance to the undercut formation during selective epitaxial growth (SEG) processes. The N2O annealed oxide tetraethyoxysilane (TEOS) oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the silicon substrate for the stacked structure. The sidewall damage is the predominant factor deteriorating the current-voltage (I-V) characteristics of the N+-P SEG diodes. When treated with a quick HF dip and followed by a low temperature desorption cleaning before the SEG process, the N+-P SEG diode, which has no perceivable undercut, shows satisfactory I-V characteristics.en_US
dc.language.isoen_USen_US
dc.titleEffects of isolation oxides on undercut formation and electrical characteristics for silicon selective epitaxial growthen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/1.1837770en_US
dc.identifier.journalJOURNAL OF THE ELECTROCHEMICAL SOCIETYen_US
dc.citation.volume144en_US
dc.citation.spage2226en_US
dc.citation.epage2230en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1997XH82800072en_US
dc.citation.woscount3en_US
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