| 標題: | Improved characteristics for Pd nanocrystal memory with stacked HfAlO-SiO2 tunnel layer |
| 作者: | Kang, Tsung-Kuei Liu, Han-Wen Wang, Fang-Hsing Lin, Cheng-Li Liao, Ta-Chuan Wu, Wen-Fa 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 關鍵字: | HfAlO-SiO2 tunnel layer;Pd nanocrystal;Thermally induced trap;Asymmetric tunnel barrier;N-2 plasma;Memory characteristic |
| 公開日期: | 1-七月-2011 |
| 摘要: | Stacked HfAlO-SiO2 tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO2 tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO2 tunnel layer. Owing to the thermally induced traps in HfAlO-SiO2 films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO2/Pd NC5/1.5 nm-HfAlO/3.5 nm-SiO2/Si structure. A N-2 plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO2. (C) 2011 Elsevier Ltd. All rights reserved. |
| URI: | http://dx.doi.org/10.1016/j.sse.2011.02.003 http://hdl.handle.net/11536/150318 |
| ISSN: | 0038-1101 |
| DOI: | 10.1016/j.sse.2011.02.003 |
| 期刊: | SOLID-STATE ELECTRONICS |
| Volume: | 61 |
| 起始頁: | 100 |
| 結束頁: | 105 |
| 顯示於類別: | 期刊論文 |

