2.4-GHz Low-Noise Direct-Conversion Receiver With Deep N-Well Vertical-NPN BJT Operating Near Cutoff Frequency

Abstract

A 2.4-GHz low-power low-noise direct-conversion receiver is demonstrated using parasitic vertical-NPN bipolar junction transistors (BJTs) in a standard 0.18-mu m CMOS process. The current switching operation of a Gilbert mixer with finite transistor cutoff frequency (f(T)) is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor f(T), the loss of the polyphase filter due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3-D realization are employed in this paper to reduce local oscillator power by 4.5 dB. At 2.4 GHz, the demonstrated receiver has conversion gain of 51 dB and noise figure of 3.2 dB with 70-kHz 1/f noise corner, while the current consumption is 4.5 mA at a 1.8-V supply.