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dc.contributor.authorLin, MCen_US
dc.contributor.authorDung, LRen_US
dc.date.accessioned2019-04-02T06:04:41Z-
dc.date.available2019-04-02T06:04:41Z-
dc.date.issued2004-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/150669-
dc.description.abstractThis paper presents a novel implementation of rank-order filtering using maskable memory. Based on a bit-serial rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank-order filtering, polarization and update. Using the memory-orient architecture, the proposed rank-order filter can. benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read, partial write, and pipelined datapath. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits. The bit-sliced read with a polarization selector allows PMM to perform polar determination while the partial write helps next-bit update. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed.en_US
dc.language.isoen_USen_US
dc.titleA maskable memory architecture for rank-order filteringen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGYen_US
dc.citation.spage453en_US
dc.citation.epage456en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000227668700114en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper