完整後設資料紀錄
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dc.contributor.authorHuang, CYen_US
dc.contributor.authorSu, HYen_US
dc.date.accessioned2019-04-02T06:04:42Z-
dc.date.available2019-04-02T06:04:42Z-
dc.date.issued2004-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/150680-
dc.description.abstractTo understand the tradeoff between the system throughput and the user fairness, in this paper, two different scheduler design concepts are discussed and evaluated based on the full-buffer data model and finite packet-call-size data model. In finite packet-call-size data model, we will show analytically and by simulation that the system throughput depends on the number of active users and the user's in-slot rates. In order to quantify the impacts, a simulation platform is developed based on IxEV-DO technology.en_US
dc.language.isoen_USen_US
dc.subjectwirelessen_US
dc.subjectCDMAen_US
dc.subjectdataen_US
dc.subject1xEV-DOen_US
dc.subject3Gen_US
dc.subjectfairnessen_US
dc.subjectscheduleren_US
dc.subjectdata modelen_US
dc.subjectsystem throughputen_US
dc.titleScheduler design issues for wireless high-speed data systemsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal8TH WORLD MULTI-CONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XIII, PROCEEDINGS: INDUSTRIAL SYSTEMSen_US
dc.citation.spage293en_US
dc.citation.epage298en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000227691200053en_US
dc.citation.woscount0en_US
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