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dc.contributor.authorPeng, Yin-Chien_US
dc.contributor.authorChen, Chien-Chihen_US
dc.contributor.authorChang, Chia-Jungen_US
dc.contributor.authorChen, Tien-Fuen_US
dc.contributor.authorYew, Pen-Chungen_US
dc.date.accessioned2019-04-02T06:04:51Z-
dc.date.available2019-04-02T06:04:51Z-
dc.date.issued2013-01-01en_US
dc.identifier.issn2474-2724en_US
dc.identifier.urihttp://hdl.handle.net/11536/150684-
dc.description.abstractFor the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.en_US
dc.language.isoen_USen_US
dc.titleCross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicoresen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT)en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000393052900067en_US
dc.citation.woscount0en_US
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