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dc.contributor.authorWu, Yan-Shiunen_US
dc.contributor.authorSu, Hong-Yanen_US
dc.contributor.authorChang, Yi-Hsiangen_US
dc.contributor.authorTopaloglu, Rasit Onuren_US
dc.contributor.authorLi, Yih-Langen_US
dc.date.accessioned2019-04-02T06:04:51Z-
dc.date.available2019-04-02T06:04:51Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2474-2724en_US
dc.identifier.urihttp://hdl.handle.net/11536/150810-
dc.description.abstractWith the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapReduce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work outperforms the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.en_US
dc.language.isoen_USen_US
dc.subjectMapReduceen_US
dc.subjectPrayer encodingen_US
dc.subjectpattern classificationen_US
dc.subjectdesign for manufacturabilityen_US
dc.titleMapReduce-Based Pattern Classification for Design Space Analysisen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000450113800052en_US
dc.citation.woscount0en_US
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