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dc.contributor.authorSung, Kuohuaen_US
dc.contributor.authorHsu, Terng-Yinen_US
dc.date.accessioned2019-04-02T06:04:48Z-
dc.date.available2019-04-02T06:04:48Z-
dc.date.issued2017-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/150829-
dc.description.abstractthis paper explains how to use a field programmable gate array (FPGA) evaluation board, which has limited resources, to build a reduced version of the OFDM baseband processor platform. The contribution in this paper is to propose conversion approaches and establish that these efficient approaches can be used to translate the design of the silicon OFDM- baseband processor into the design of a FPGA. The innovation in this paper is in providing a simple and effective way to accomplish a pipelined divider on an FPGA.en_US
dc.language.isoen_USen_US
dc.subjectMIMO: Multpile-Input and Multiple-Outputen_US
dc.subjectIP: Intellectual Propertyen_US
dc.subjectOFDM: Orthogonal Frequency-Division Multiplexingen_US
dc.subjectLUT: Look-Up Tableen_US
dc.subjectMMCM: Mixed-Mode Clock Manageren_US
dc.subjectOR1200: OpenRISC 1200en_US
dc.subjectCE: Clock Enableen_US
dc.subjectRALU: Reconfigurable Arithmatic Logic Uniten_US
dc.subjectRecMem: Reconfigurable Memoryen_US
dc.subjectPCIE: Peripheral Component Interconnect Expressen_US
dc.titleFPGA Implementation of OFDM Baseband Processoren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 IEEE CONFERENCE ON DEPENDABLE AND SECURE COMPUTINGen_US
dc.citation.spage466en_US
dc.citation.epage467en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000450296400064en_US
dc.citation.woscount0en_US
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