完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, Yuan-Sheng | en_US |
dc.contributor.author | Chen, Wei-Zen | en_US |
dc.date.accessioned | 2019-04-02T06:04:28Z | - |
dc.date.available | 2019-04-02T06:04:28Z | - |
dc.date.issued | 2018-01-01 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/150859 | - |
dc.description.abstract | A single chip optical receiver comprising of a font-end amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 2(31)-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10(-12) (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm(2). It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | optical receiver | en_US |
dc.subject | baud rate CDR | en_US |
dc.subject | demultiplexer | en_US |
dc.title | A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000451218700148 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |