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dc.contributor.authorLee, Yuan-Shengen_US
dc.contributor.authorChen, Wei-Zenen_US
dc.date.accessioned2019-04-02T06:04:28Z-
dc.date.available2019-04-02T06:04:28Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/150859-
dc.description.abstractA single chip optical receiver comprising of a font-end amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 2(31)-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10(-12) (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm(2). It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.en_US
dc.language.isoen_USen_US
dc.subjectoptical receiveren_US
dc.subjectbaud rate CDRen_US
dc.subjectdemultiplexeren_US
dc.titleA 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recoveryen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000451218700148en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper