完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHong, Hao-Chiaoen_US
dc.contributor.authorChiu, Yien_US
dc.date.accessioned2019-04-02T06:04:26Z-
dc.date.available2019-04-02T06:04:26Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/150866-
dc.description.abstractThis paper presents a 10-bit SAR ADC operating at a supply voltage (VDD) of 0.225 V and down to 0.2 V for self-sustainable IoT applications. We propose an ultra-low VDD temperature-compensated bias current generator for biasing the comparator against temperature variation to address the temperature-dependent issue of the MOSFETs operating in the subthreshold region. In addition, the design fixes the positive input terminal of the comparator at VDD to bias the input transistor pair of the comparator with a sufficient voltage headroom at such a low VDD. The double-boosted with leakage reduction sampling switch is also proposed to address the severe leakage issue at low sampling rates. A test chip has been fabricated in 180-nm CMOS. The ADC core occupies only 0.024 mm(2). Measurement results show that at 0.225V, the DNL and INL are within +1.04/-0.66 and +0.97/-1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR with the Nyquist input frequency is 49.8 dB at 450 S/s and 0.225V. The whole ADC totally consumes 0.85 nW at 0.225 V including the circuit leakages. It corresponds to an FoM of 8.0 fJ/conv.-step.en_US
dc.language.isoen_USen_US
dc.titleA 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000451218702018en_US
dc.citation.woscount0en_US
顯示於類別:會議論文