Very low noise in 90nm node RF MOSFETs using a new layout

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DC 欄位	值	語言
dc.contributor.author	Kao, H. L.	en_US
dc.contributor.author	Chin, Albert	en_US
dc.contributor.author	Liao, C. C.	en_US
dc.contributor.author	McAlister, S. P.	en_US
dc.date.accessioned	2019-04-02T06:04:44Z	-
dc.date.available	2019-04-02T06:04:44Z	-
dc.date.issued	2007-01-01	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/SMIC.2007.322765	en_US
dc.identifier.uri	http://hdl.handle.net/11536/150924	-
dc.description.abstract	We have directly measured a record low minimum noise figure (NFmin) of 0.46 dB at 10 GM, along with a high 16.6 dB Associated Gain, in an 8-finger 90 nm node MOSFET (L-G = 65nm) without de-embedding. At 18 GHz, NFmin was 0.83 dB with 13.5 dB gain. This was achieved using a microstrip line layout to screen the RF noise generated by the lossy substrate.	en_US
dc.language.iso	en_US	en_US
dc.subject	RF noise	en_US
dc.subject	f(T)	en_US
dc.subject	associated gain	en_US
dc.subject	MOSFET	en_US
dc.title	Very low noise in 90nm node RF MOSFETs using a new layout	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/SMIC.2007.322765	en_US
dc.identifier.journal	2007 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS	en_US
dc.citation.spage	44	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000245461300011	en_US
dc.citation.woscount	0	en_US
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