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dc.contributor.authorSung, P. -J.en_US
dc.contributor.authorChang, C. -Y.en_US
dc.contributor.authorChen, L. -Y.en_US
dc.contributor.authorKao, K. -H.en_US
dc.contributor.authorSu, C. -J.en_US
dc.contributor.authorLiao, T. -H.en_US
dc.contributor.authorFang, C. -C.en_US
dc.contributor.authorWang, C. -J.en_US
dc.contributor.authorHong, T. -C.en_US
dc.contributor.authorJao, C. -Y.en_US
dc.contributor.authorHsu, H. -S.en_US
dc.contributor.authorLuo, S. -X.en_US
dc.contributor.authorWang, Y. -S.en_US
dc.contributor.authorHuang, H. -F.en_US
dc.contributor.authorLi, J. -H.en_US
dc.contributor.authorHuang, Y. -C.en_US
dc.contributor.authorHsueh, F. -K.en_US
dc.contributor.authorWu, C. -T.en_US
dc.contributor.authorHuang, Y. -M.en_US
dc.contributor.authorHou, F. -J.en_US
dc.contributor.authorLuo, G. -L.en_US
dc.contributor.authorHuang, Y. -C.en_US
dc.contributor.authorShen, Y. -L.en_US
dc.contributor.authorMa, W. C. -Y.en_US
dc.contributor.authorHuang, K. -P.en_US
dc.contributor.authorLin, K. -L.en_US
dc.contributor.authorSamukawa, S.en_US
dc.contributor.authorLi, Y.en_US
dc.contributor.authorHuang, G. -Wen_US
dc.contributor.authorLee, Y. -J.en_US
dc.contributor.authorLi, J. -Y.en_US
dc.contributor.authorWu, W. -F.en_US
dc.contributor.authorShieh, J. -M.en_US
dc.contributor.authorChao, T. -S.en_US
dc.contributor.authorYeh, W. -K.en_US
dc.contributor.authorWang, Y. -H.en_US
dc.date.accessioned2019-04-02T06:04:37Z-
dc.date.available2019-04-02T06:04:37Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2380-9248en_US
dc.identifier.urihttp://hdl.handle.net/11536/151103-
dc.description.abstractFor the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 degrees C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.en_US
dc.language.isoen_USen_US
dc.titleVoltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000459882300074en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper