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dc.contributor.authorHuang, Juinn-Daren_US
dc.contributor.authorChen, Yi-Hangen_US
dc.contributor.authorHo, Ya-Chienen_US
dc.date.accessioned2014-12-08T15:21:18Z-
dc.date.available2014-12-08T15:21:18Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-4244-7516-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/15114-
dc.description.abstractAs fabrication process exploits even deeper submicron technology, global interconnect delay is becoming one of the most critical performance obstacles in system-on-chip (SoC) designs nowadays. Recent years latency-insensitive system (LIS), which enables multicycle communication to tolerate variant interconnect delay without substantially modifying pre-designed IP cores, has been proposed to conquer this issue. However, imbalanced interconnect latency and communication back-pressure residing in an LIS still degrade system throughput. In this paper, we present a throughput optimization technique with minimal queue insertion. We first model a given LIS as a quantitative graph (QG), which can be further compacted using the proposed techniques, so that much bigger problems can be handled. On top of QG, the optimal solution with minimal queue size can be achieved through integer linear programming based on the proposed constraint formulation in an acceptable runtime. The experimental results show that our approach can deal with moderately large systems in a reasonable runtime and save about 28% of queues compared to the prior art.en_US
dc.language.isoen_USen_US
dc.titleThroughput Optimization for Latency-Insensitive System with Minimal Queue Insertionen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000299427300117-
Appears in Collections:Conferences Paper