標題: | Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis |
作者: | Lee, Chi-Hui Shih, Che-Hua Huang, Juinn-Dar Jou, Jing-Yang 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2011 |
摘要: | This paper presents a formal method for equivalence checking between the descriptions before and after scheduling in high-level synthesis (HLS). Both descriptions are represented by finite state machine with datapaths (FSMDs) and are then characterized through finite sets of paths. The main target of our proposed method is to verify scheduling employing code transformations - such as speculation and common subexpression extraction (CSE), across basic block (BB) boundaries - which have not been properly addressed in the past. Nevertheless, our method can verify typical BB-based and path-based scheduling as well. The experimental results demonstrate that the proposed method can indeed outperform an existing state-of-the-art equivalence checking algorithm. |
URI: | http://hdl.handle.net/11536/15117 |
ISBN: | 978-1-4244-7516-2 |
期刊: | 2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) |
顯示於類別: | 會議論文 |