Multiloop Interleaved Control for Two-Switch Two-Capacitor Three-level SMR without Capacitor Voltage Balancing Loop

Abstract

Compared with the conventional single-switch single-capacitor switching-mode rectifier (SMR), two-switch two-capacitor three-level boost-type SMR has advantage of low voltage stress, low current ripple and low switching loss. Due to the capacitor in series, the balance between two capacitor voltage is necessary. In order to obtain PFC function and keep the balance between capacitor voltages, additional voltage balancing loop is included into the conventional multiloop control to generate the two switching signals in the literature. But the complexity is the main disadvantages. In this paper, conventional multiloop with common interleaved control is proposed to generate the two switching signal without voltage balancing loop and without sensing any capacitor voltage. The proposed multiloop interleaved control is digitally implemented in a FPGA-based system. From the provided simulated and the experimental result, the PFC function is obtained and the capacitor voltage are equal to each other. It shows that the proposed multiloop interleaved control operates stably.