標題: | A Novel LTPS-TFT-Based Charge-Trapping Memory Device with Field-Enhanced Nanowire Structure |
作者: | Liao, Ta-Chuan Chen, Sheng-Kai Yu, Ming H. Wu, Chun-Yu Kang, Tsung-Kuei Chien, Feng-Tso Liu, Yen-Ting Lin, Chia-Min Cheng, Huang-Chung 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2009 |
摘要: | A novel gate-all-around low-temperature poly-Si (LIPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster PIE speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications. |
URI: | http://hdl.handle.net/11536/15149 |
ISBN: | 978-1-4244-5639-0 |
期刊: | 2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING |
起始頁: | 190 |
結束頁: | 193 |
顯示於類別: | 會議論文 |