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dc.contributor.authorCHANG EDWARD YIen_US
dc.contributor.authorLIU SHIH-CHIENen_US
dc.contributor.authorHUANG CHUNG-KAIen_US
dc.contributor.authorWU CHIA-HSUNen_US
dc.contributor.authorHAN PING-CHENGen_US
dc.contributor.authorLIN YUEH-CHINen_US
dc.contributor.authorHSIEH TING-ENen_US
dc.contributor.authorChang, Edward Yien_US
dc.contributor.authorLiu, Shih-Chienen_US
dc.contributor.authorHuang, Chung-Kaien_US
dc.contributor.authorWu, Chia-Hsunen_US
dc.contributor.authorHan, Ping-Chengen_US
dc.contributor.authorLin, Yueh-Chinen_US
dc.contributor.authorHsieh, Ting-Enen_US
dc.date.accessioned2019-04-11T06:20:45Z-
dc.date.available2019-04-11T06:20:45Z-
dc.date.issued2018-06-21en_US
dc.identifier.govdocH01L029/792en_US
dc.identifier.govdocH01L021/336en_US
dc.identifier.govdocH01L029/12en_US
dc.identifier.govdocH01L029/778en_US
dc.identifier.urihttp://hdl.handle.net/11536/151534-
dc.description.abstractA semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material.en_US
dc.language.isoen_USen_US
dc.titleHalbleitervorrichtung und Verfahren zur Herstellung derselbenen_US
dc.typePatentsen_US
dc.citation.patentcountryWSAen_US
dc.citation.patentnumberDE102017119774A1en_US
Appears in Collections:Patents