完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHANG EDWARD YI | en_US |
dc.contributor.author | LIU SHIH-CHIEN | en_US |
dc.contributor.author | HUANG CHUNG-KAI | en_US |
dc.contributor.author | WU CHIA-HSUN | en_US |
dc.contributor.author | HAN PING-CHENG | en_US |
dc.contributor.author | LIN YUEH-CHIN | en_US |
dc.contributor.author | HSIEH TING-EN | en_US |
dc.contributor.author | Chang, Edward Yi | en_US |
dc.contributor.author | Liu, Shih-Chien | en_US |
dc.contributor.author | Huang, Chung-Kai | en_US |
dc.contributor.author | Wu, Chia-Hsun | en_US |
dc.contributor.author | Han, Ping-Cheng | en_US |
dc.contributor.author | Lin, Yueh-Chin | en_US |
dc.contributor.author | Hsieh, Ting-En | en_US |
dc.date.accessioned | 2019-04-11T06:20:45Z | - |
dc.date.available | 2019-04-11T06:20:45Z | - |
dc.date.issued | 2018-06-21 | en_US |
dc.identifier.govdoc | H01L029/792 | en_US |
dc.identifier.govdoc | H01L021/336 | en_US |
dc.identifier.govdoc | H01L029/12 | en_US |
dc.identifier.govdoc | H01L029/778 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/151534 | - |
dc.description.abstract | A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Halbleitervorrichtung und Verfahren zur Herstellung derselben | en_US |
dc.type | Patents | en_US |
dc.citation.patentcountry | WSA | en_US |
dc.citation.patentnumber | DE102017119774A1 | en_US |
顯示於類別: | 專利資料 |