An Area-efficient High-accuracy Prediction-based CABAC Decoder Architecture for H.264/AVC

Abstract

This paper proposed a high-accuracy prediction scheme and area-efficient CABAC decoder architecture for H. 264 video decoder. To alleviate hardware cost and keep high throughput, we propose the prediction process and optimize the memory system. In particular, simulation results show that the proposed prediction-based CABAC decoder module achieves over 90% hit rate and requires only 16K logic gates with 3,360 bits SRAM by UMC 90 nm technology. The proposed architecture operates on 150 MHz frequency (Max. 249 MHz) for realizing 1080HD video playback at 30 fps, which can achieve Level 5.0 MP in tiny gate count.