High Resolution Comparator Design For RF Imager

Abstract

This paper proposes a design of high resolution regenerative latch based comparator for Multi Ramp Multi slope ADC of RF 3D imager. The minimum sense voltage for the design comparator is 500nV. A wide swing-self biased fully differential folded cascode amplifier used as analog front end for regenerative latch. Due to fully differential architecture of the comparator noise immunity is high. Simulation is done by using TSMC 0.18um with 1.8V supply. The total Power consumption of design comparator is 0.842mW and total delay is 11 mu s.