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dc.contributor.authorPandey, Rajeev Kumaren_US
dc.contributor.authorPandey, Sanjeev Kumaren_US
dc.date.accessioned2019-05-02T00:26:46Z-
dc.date.available2019-05-02T00:26:46Z-
dc.date.issued2018-01-01en_US
dc.identifier.isbn978-1-5386-7336-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/151708-
dc.description.abstractThis paper proposes a design of high resolution regenerative latch based comparator for Multi Ramp Multi slope ADC of RF 3D imager. The minimum sense voltage for the design comparator is 500nV. A wide swing-self biased fully differential folded cascode amplifier used as analog front end for regenerative latch. Due to fully differential architecture of the comparator noise immunity is high. Simulation is done by using TSMC 0.18um with 1.8V supply. The total Power consumption of design comparator is 0.842mW and total delay is 11 mu s.en_US
dc.language.isoen_USen_US
dc.subjectRF imageren_US
dc.subjectCascode Amplifieren_US
dc.subjectSR Latchen_US
dc.subjectRegenerative Latchen_US
dc.subjectComparatoren_US
dc.titleHigh Resolution Comparator Design For RF Imageren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2018 IEEE RECENT ADVANCES IN INTELLIGENT COMPUTATIONAL SYSTEMS (RAICS)en_US
dc.citation.spage65en_US
dc.citation.epage69en_US
dc.contributor.department電機資訊國際碩士學位學程zh_TW
dc.contributor.departmentEECS International Graduate Program-Masteren_US
dc.identifier.wosnumberWOS:000462370200014en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper