標題: A Low Power Independent Component Analysis Processor in 90nm CMOS Technology for EEG Signal Processing Systems
作者: Chen, Chiu-Kuo
Wang, Yi-Yuan
Hsieh, Zong-Han
Chua, Ericson
Fang, Wai-Chi
Jung, Tzyy-Ping
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2011
摘要: This paper presents a low-power VLSI implementation of a 4-channel independent component analysis (ICA) processor for portable EEG signal processing applications. The low-power scheme employed for this ICA chip is based on power gating and clock gating by utilizing Cadence common power flow (CPF) low-power methodology and also according to the characteristics of ICA training behavior using different training window sizes. The proposed low power ICA processor can separate EEG and mixed EEG-like super-Gaussian signals in real time. The chip can be operated at up to 60MHz working frequency and a maximum sampling rate of 9.394 KHz for EEG signals. The power consumption of this chip is 0.690 mW during training under the condition of 0.9V supply voltage and 10 MHz operating frequency using UMC 90nm High-Vt CMOS technology. The total chip area is 1230 x 1230 mu m(2).
URI: http://hdl.handle.net/11536/15172
ISBN: 978-1-4244-9474-3
ISSN: 0271-4302
期刊: 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
起始頁: 801
結束頁: 804
Appears in Collections:Conferences Paper