完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, Kai-Yen | en_US |
dc.contributor.author | Ho, Yun-Lung | en_US |
dc.contributor.author | Huang, Yu-De | en_US |
dc.contributor.author | Fang, Wai-Chi | en_US |
dc.date.accessioned | 2019-06-03T01:09:15Z | - |
dc.date.available | 2019-06-03T01:09:15Z | - |
dc.date.issued | 2018-01-01 | en_US |
dc.identifier.isbn | 978-1-5386-6318-9 | en_US |
dc.identifier.issn | 1520-6130 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152002 | - |
dc.description.abstract | In this paper, we propose a system-on-chip(SOC) design of highly effective multi-channel real-time EEG signal processing system based on Online-Recursive Independent Component Analysis (ORICA) algorithm implemented using TSMC's 28nm CMOS technology. In this chip, concepts of system-on-chip (SOC) design and effective system integration technique are well-combined together to realize a highly miniaturized realtime EEG processing system.. The core area and total power consumption of the chip are respectively 1246* 1246 mu m2 and 25.03mW. The chip operations were validated by ADVANTEST V93000 PS1600 and the results obtained match with the software simulation. The average correlation coefficient between original source signals and extracted ORICA signals reaches 0.9572. Eye blink artifact, and facial muscle artifact will be removed automatically. Producing a pure EEG signal is beneficial for realtime data analysis; therefore, this chip design can enhance the reliability and feasibility of EEG-related applications, such as BCI, medical diagnosis and depth of anesthesia detection. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Real Time EEG | en_US |
dc.subject | EEG signal processing | en_US |
dc.subject | CMOS 28nm tehnology | en_US |
dc.subject | ORICA algorithm | en_US |
dc.subject | de-artifact process | en_US |
dc.title | A 16 Channel Real-Time EEG Processing Based on ORICA Algorithm using 28nm CMOS Technology | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS) | en_US |
dc.citation.spage | 269 | en_US |
dc.citation.epage | 274 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000465106800046 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |