Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Tang, Y. -T | en_US |
dc.contributor.author | Su, C. -J. | en_US |
dc.contributor.author | Wang, Y. -S. | en_US |
dc.contributor.author | Kao, K. -H. | en_US |
dc.contributor.author | Wu, T. -L. | en_US |
dc.contributor.author | Sung, P. -J. | en_US |
dc.contributor.author | Hou, F. -J. | en_US |
dc.contributor.author | Wang, C. -J. | en_US |
dc.contributor.author | Yeh, M. -S. | en_US |
dc.contributor.author | Lee, Y. -J. | en_US |
dc.contributor.author | Wu, W. -F. | en_US |
dc.contributor.author | Huang, G. -W. | en_US |
dc.contributor.author | Shieh, J. -M. | en_US |
dc.contributor.author | Yeh, W. -K. | en_US |
dc.contributor.author | Wang, Y. -H. | en_US |
dc.date.accessioned | 2019-06-03T01:09:17Z | - |
dc.date.available | 2019-06-03T01:09:17Z | - |
dc.date.issued | 2018-01-01 | en_US |
dc.identifier.isbn | 978-1-5386-4218-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152027 | - |
dc.description.abstract | The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (L-G=10nm) NC-FET with thin FE layer (T-FE similar to 2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | en_US |
dc.citation.spage | 45 | en_US |
dc.citation.epage | 46 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000465075200015 | en_US |
dc.citation.woscount | 1 | en_US |
Appears in Collections: | Conferences Paper |