完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liao, P. H. | en_US |
dc.contributor.author | Kuo, M. H. | en_US |
dc.contributor.author | Tien, C. W. | en_US |
dc.contributor.author | Chang, Y. L. | en_US |
dc.contributor.author | Hong, P. Y. | en_US |
dc.contributor.author | George, T. | en_US |
dc.contributor.author | Lin, H. C. | en_US |
dc.contributor.author | Li, P. W. | en_US |
dc.date.accessioned | 2019-06-03T01:09:17Z | - |
dc.date.available | 2019-06-03T01:09:17Z | - |
dc.date.issued | 2018-01-01 | en_US |
dc.identifier.isbn | 978-1-5386-4218-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152030 | - |
dc.description.abstract | We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO2/Si1-xGex channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5-90nm), SiO2 thickness (2-4nm), and Ge content (x = 0.65-0.85) and strain engineering (epsilon(comp) = 1-3%) of the Si1-xGex are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. L-G of 75nm JL n-FETs feature I-ON/I-OFF > 5x10(8), I-ON > 500 mu A/mu m at V-DS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity > 1,000A/W and current gain linearity ranging from nW-mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300-1600nm (NUV-NIR) are observed on 5-100nm Ge NPs. Our gate stack of Ge NP/SiO2/Si1-xGex enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Ge | en_US |
dc.subject | junctionless | en_US |
dc.subject | phototransistor | en_US |
dc.subject | monolithic integration | en_US |
dc.title | Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | en_US |
dc.citation.spage | 157 | en_US |
dc.citation.epage | 158 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000465075200059 | en_US |
dc.citation.woscount | 1 | en_US |
顯示於類別: | 會議論文 |