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dc.contributor.authorChung, Steve S.en_US
dc.date.accessioned2019-09-02T07:45:40Z-
dc.date.available2019-09-02T07:45:40Z-
dc.date.issued2016-01-01en_US
dc.identifier.isbn978-1-4673-9719-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/152550-
dc.description.abstractThe breakdown path which leads to the soft- and hard-breakdown in a MOSFET device can be identified from the experiment. It carries similar concept of the filament formation in RRAM device. Basically, RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path, i.e., from the leakage by measuring the transistor's I-g current as a function of time. In CMOS, these traps can be considered as the leakage path in the gate dielectrics which eventually cause the final hard-breakdown. In RRAM device, these traps are closely related to the soft breakdown which is the key element of filament formation. The RTN analysis can also be utilized to examine the influences of RTN traps on the SBD paths. The instability of the switching resistance, caused by the traps will be illustrated.en_US
dc.language.isoen_USen_US
dc.titleThe Understanding of Breakdown Path in Both High-k Metal-Gate CMOS and Resistance RAM by the RTN Measurementen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)en_US
dc.citation.spage428en_US
dc.citation.epage431en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000478951000118en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper