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dc.contributor.authorWang, I-Tingen_US
dc.contributor.authorChou, Teyuhen_US
dc.contributor.authorChiu, Li-Wenen_US
dc.contributor.authorChang, Chih-Chengen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.date.accessioned2019-09-02T07:45:40Z-
dc.date.available2019-09-02T07:45:40Z-
dc.date.issued2016-01-01en_US
dc.identifier.isbn978-1-4673-9719-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/152552-
dc.description.abstractTo facilitate the development of low-cost, low-power, and high-density hardware neural networks, we have successfully developed a Ta/TaOx/TiO2/Ti RRAM-based synaptic device. The device exhibits numerous synaptic functions resembling those in biological synapses, including synaptic plasticity of potentiation and depression, spike-timing dependent plasticity, paired-pulse facilitation and a transition from short-term to long-term memory. We further demonstrate 3D high-density, high-connectivity integration of the Ta/TaOx/TiO2/Ti device, and the device exhibits excellent uniformity among interlayer and intralayer cells in a 4 x 4 3D two-layer cross-point array. Finally, we investigate the influence of nonlinearity of synaptic weight updates on neuromorphic computing. A state-independent training scheme is proposed to improve linearity and fault tolerance of training accuracy.en_US
dc.language.isoen_USen_US
dc.titleDevelopment of Three-Dimensional Synaptic Device and Neuromorphic Computing Hardwareen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)en_US
dc.citation.spage620en_US
dc.citation.epage623en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000478951000171en_US
dc.citation.woscount0en_US
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