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dc.contributor.authorChung, Ya-Chinen_US
dc.contributor.authorCheng, Po-Hsiangen_US
dc.contributor.authorLiu, Chih-Weien_US
dc.date.accessioned2019-09-02T07:45:41Z-
dc.date.available2019-09-02T07:45:41Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-0655-7en_US
dc.identifier.issn2474-2724en_US
dc.identifier.urihttp://hdl.handle.net/11536/152559-
dc.description.abstractWe use FFT-based convolution in frequency domain to reduce computational complexity in CNNs. The properties of conjugate symmetry and down-sampling is adopted to further reduce complexity. By eliminating filter weights in CNNs that can save computational requirement but lead to accuracy loss. The simulation result reveals that eliminating filter weights in frequency domain is more accurate than that in time domain. With the proposed design synthesized by TSMC 90 nm CMOS technology, the total latency, power and energy are considerably competitive. As a result, our FFT-based CNN accelerator is energy-efficient.en_US
dc.language.isoen_USen_US
dc.titleEnergy Efficient CNN Inference Accelerator using Fast Fourier Transformen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000480385400016en_US
dc.citation.woscount0en_US
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