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dc.contributor.authorNg, Chee-Kiten_US
dc.contributor.authorLin, Yu-Chunen_US
dc.contributor.authorJou, Shyh-Tyeen_US
dc.date.accessioned2019-09-02T07:45:41Z-
dc.date.available2019-09-02T07:45:41Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-0655-7en_US
dc.identifier.issn2474-2724en_US
dc.identifier.urihttp://hdl.handle.net/11536/152562-
dc.description.abstractA 50Gbls all-digital adaptive noise-suppression (NS) feed-forward equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) serial link systems with SNR based power management scheme is presented. Based on a parallel extended incremental coefficients-lookahead scheme (EICL), we propose a reconfigurable Dual Data paths Self-Lookahead Filter (DD-SLF) for ADFE. SNR-power management skill is adopted to adaptively adjust the hardware configuration in different channel environment and SNR to achieve optimum energy efficiency. The whole equalizer which operates at 1 GHz system clock rate with 50 parallelisms is implemented in 40nm CMOS technology with a core area 0.38mm(2). The equalizer with 50Gb/s throughput rate achieves 2.6pJ/bit energy efficiency under 0.81V supply measurement results.en_US
dc.language.isoen_USen_US
dc.subjectserial linken_US
dc.subject2-PAM digital adaptive decision feedback equalizeren_US
dc.subjectSNR power managementen_US
dc.titleA 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systemsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000480385400045en_US
dc.citation.woscount0en_US
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