完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Joi, Aniruddha | en_US |
dc.contributor.author | Venkatraman, Kailash | en_US |
dc.contributor.author | Tso, Kuang-Chih | en_US |
dc.contributor.author | Dictus, Dries | en_US |
dc.contributor.author | Dordi, Yezdi | en_US |
dc.contributor.author | Wu, Pu-Wei | en_US |
dc.contributor.author | Pao, Chih-Wen | en_US |
dc.contributor.author | Akolkar, Rohan | en_US |
dc.date.accessioned | 2019-10-05T00:08:44Z | - |
dc.date.available | 2019-10-05T00:08:44Z | - |
dc.date.issued | 2019-08-28 | en_US |
dc.identifier.issn | 2162-8769 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1149/2.0181909jss | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152838 | - |
dc.description.abstract | A novel interface engineering approach, utilizing electrochemical atomic layer deposition (e-ALD) of Cu(Zn) on a Ru liner, is presented for enabling the metallization of sub-10 nm interconnects in future semiconductor devices. Upon thermal treatment, Zn present in the e-ALD Cu layer at similar to 0.8 at.% is shown to diffuse through the Ru liner and react with the SiO2 to form a Zn-silicate layer at the Ru-SiO2 interface. This 'self-forming' interfacial layer provides adhesion enhancement to the Ru-SiO2 interface and serves as a diffusion barrier retarding Cu diffusion into the SiO2 layer while enabling void-free gap-filling of high aspect ratio trench structures. Absorption Near-Edge Spectroscopy and Extended X-ray Absorption Fine Structure analyses confirm that the self-formed barrier layer is composed primarily of Zn2SiO4. The interface engineering approach utilizing Cu(Zn) presented herein offers several potential advantages over traditional Mn-based self-forming barrier approaches, i.e., scalability to narrower dimensions and minimal impact to interconnect resistance. (C) The Author(s) 2019. Published by ECS. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Interface Engineering Strategy Utilizing Electrochemical ALD of Cu-Zn for Enabling Metallization of Sub-10 nm Semiconductor Device Nodes | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1149/2.0181909jss | en_US |
dc.identifier.journal | ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY | en_US |
dc.citation.volume | 8 | en_US |
dc.citation.issue | 9 | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000483299700001 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |