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dc.contributor.authorChang, Kuo-Weien_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.date.accessioned2019-10-05T00:09:47Z-
dc.date.available2019-10-05T00:09:47Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-0397-6en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/152960-
dc.description.abstractHardware accelerator for convolution neural network (CNNs) enables real time applications of artificial intelligence technology. However, most of the accelerators only support dense CNN computations or suffers complex control to support fine grained sparse networks. To solve above problem, this paper presents an efficient CNN accelerator with 1-D vector broadcasted input to support both dense network as well as vector sparse network with the same hardware and low overhead. The presented design achieves 1.93X speedup over the dense CNN computations.en_US
dc.language.isoen_USen_US
dc.subjectHardware designen_US
dc.subjectconvolution neural networks (CNNs)en_US
dc.subjectsparse CNNsen_US
dc.titleVSCNN: Convolution Neural Network Accelerator With Vector Sparsityen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000483076401148en_US
dc.citation.woscount0en_US
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