完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Kuo-Wei | en_US |
dc.contributor.author | Chang, Tian-Sheuan | en_US |
dc.date.accessioned | 2019-10-05T00:09:47Z | - |
dc.date.available | 2019-10-05T00:09:47Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-0397-6 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152960 | - |
dc.description.abstract | Hardware accelerator for convolution neural network (CNNs) enables real time applications of artificial intelligence technology. However, most of the accelerators only support dense CNN computations or suffers complex control to support fine grained sparse networks. To solve above problem, this paper presents an efficient CNN accelerator with 1-D vector broadcasted input to support both dense network as well as vector sparse network with the same hardware and low overhead. The presented design achieves 1.93X speedup over the dense CNN computations. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Hardware design | en_US |
dc.subject | convolution neural networks (CNNs) | en_US |
dc.subject | sparse CNNs | en_US |
dc.title | VSCNN: Convolution Neural Network Accelerator With Vector Sparsity | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000483076401148 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |