Multiple Correlation Estimation Based Digital Background Calibration Scheme for Pipelined ADCs

Abstract

A digital background calibration scheme for calibrating the linear, third-order, and fifth-order nonlinear gain errors of the residue amplifiers (RAs) in pipelined ADCs is proposed. By alternating injecting three pseudo-random binary sequences (PRBS) with designated weights to the RA through the sub-DAC, multiple correlations of the nonlinearity-corrected backend ADC's outputs and the injected PRBS signals are computed by digital circuits to estimate the calibration parameters according to the proposed multiple correlation estimation (MCE) method. Three least-mean-square (LMS) loops are used to acquire and track the optimal values of the calibration parameters in background so as to vanish all the errors in the ADC's output. Simulation results of a 14-bit pipelined ADC show the proposed calibration scheme improves the SNDR of the ADC from 31.2 dB to 80.4 dB. The proposed calibration scheme relaxes the design requirements of the RAs, making it well suit the design in advanced technology.