完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hung, Tao-Yi | en_US |
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.date.accessioned | 2019-10-05T00:09:47Z | - |
dc.date.available | 2019-10-05T00:09:47Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-0397-6 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152967 | - |
dc.description.abstract | Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-mu m CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the posith e-to-V-ss stress and 5 kV under the negative-to-V-ss stress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | ESD protection design | en_US |
dc.subject | transient detection circuit | en_US |
dc.subject | high-linearity switch | en_US |
dc.subject | power-rail ESD clamp circuit | en_US |
dc.subject | SPDT | en_US |
dc.subject | T/R switch | en_US |
dc.title | ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000483076403002 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |