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dc.contributor.authorDu, Yuanen_US
dc.contributor.authorDu, Lien_US
dc.contributor.authorGu, Xuefengen_US
dc.contributor.authorDu, Jieqiongen_US
dc.contributor.authorWang, X. Shawnen_US
dc.contributor.authorHu, Boyuen_US
dc.contributor.authorJiang, Mingzheen_US
dc.contributor.authorChen, Xiaoliangen_US
dc.contributor.authorIyer, Subramanian S.en_US
dc.contributor.authorChang, Mau-Chung Franken_US
dc.date.accessioned2019-12-13T01:09:58Z-
dc.date.available2019-12-13T01:09:58Z-
dc.date.issued2019-10-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2018.2859237en_US
dc.identifier.urihttp://hdl.handle.net/11536/153049-
dc.description.abstractAn analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. By implementing the sequential analog fabric, the engine's mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm(2). The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem-classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.en_US
dc.language.isoen_USen_US
dc.subjectAnalog computing engineen_US
dc.subjectartificial neural networksen_US
dc.subjectcharge-trap transistors (CTTs)en_US
dc.subjectfully connected neural networks (FCNNs)en_US
dc.titleAn Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)en_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2018.2859237en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume38en_US
dc.citation.issue10en_US
dc.citation.spage1811en_US
dc.citation.epage1819en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000487193400003en_US
dc.citation.woscount1en_US
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