完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Du, Yuan | en_US |
dc.contributor.author | Du, Li | en_US |
dc.contributor.author | Gu, Xuefeng | en_US |
dc.contributor.author | Du, Jieqiong | en_US |
dc.contributor.author | Wang, X. Shawn | en_US |
dc.contributor.author | Hu, Boyu | en_US |
dc.contributor.author | Jiang, Mingzhe | en_US |
dc.contributor.author | Chen, Xiaoliang | en_US |
dc.contributor.author | Iyer, Subramanian S. | en_US |
dc.contributor.author | Chang, Mau-Chung Frank | en_US |
dc.date.accessioned | 2019-12-13T01:09:58Z | - |
dc.date.available | 2019-12-13T01:09:58Z | - |
dc.date.issued | 2019-10-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCAD.2018.2859237 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/153049 | - |
dc.description.abstract | An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. By implementing the sequential analog fabric, the engine's mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm(2). The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem-classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Analog computing engine | en_US |
dc.subject | artificial neural networks | en_US |
dc.subject | charge-trap transistors (CTTs) | en_US |
dc.subject | fully connected neural networks (FCNNs) | en_US |
dc.title | An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT) | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCAD.2018.2859237 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 38 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 1811 | en_US |
dc.citation.epage | 1819 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000487193400003 | en_US |
dc.citation.woscount | 1 | en_US |
顯示於類別: | 期刊論文 |