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dc.contributor.authorChen, Chun Hanen_US
dc.contributor.authorParashar, Paragen_US
dc.contributor.authorAkbar, Chandnien_US
dc.contributor.authorFu, Sze Mingen_US
dc.contributor.authorSyu, Ming-Yingen_US
dc.contributor.authorLin, Alberten_US
dc.date.accessioned2019-12-13T01:09:59Z-
dc.date.available2019-12-13T01:09:59Z-
dc.date.issued2019-01-01en_US
dc.identifier.issn2169-3536en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ACCESS.2019.2940130en_US
dc.identifier.urihttp://hdl.handle.net/11536/153058-
dc.description.abstractWith the fast scaling-down and evolution of integrated circuit (IC) manufacturing technology, the fabrication process becomes highly complex, and the experimental cost of the processes is significantly elevated. Therefore, in many cases, it is very costly to obtain a sufficient amount of experimental data. To develop an efficient method to predict the results of semiconductor experiments with a small amount of known data, we use a novel method based on Bayesian framework with the prior distribution constructed by technology computer-aided-design (TCAD) physical models. This method combines the advantages of statistical models and physical models in the aspect that TCAD can provide visionary guidance on an experiment when a limited amount of experimental data is available, and a machine learning model can account for subtle anomalous effects. Specifically, we use aspect ratio dependent etching (ARDE) phenomenon as an example and use variational inference with Kullback-Leibler divergence minimization to achieve the approximation to the posterior distribution. The relation between etching process input parameters and etching depth is learned using the Bayesian neural network with TCAD priors. Using this method with 35 neurons per hidden layer, mean square error (MSE) in the test set is reduced from 0.2896 to 0.0175, 0.058 to 0.0183, 0.0563 to 0.0188, 0.058 to 0.019 for partition =10, 20, 30, 40, respectively, reference to the baseline BNN where a regular normal distribution prior with zero mean and unity standard deviation N(0,1) is used.en_US
dc.language.isoen_USen_US
dc.subjectArtificial intelligenceen_US
dc.subjectmanufacturingen_US
dc.subjectphysicsen_US
dc.subjectBayesian methodsen_US
dc.subjectintelligent manufacturing systemsen_US
dc.titlePhysics-Prior Bayesian Neural Networks in Semiconductor Processingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ACCESS.2019.2940130en_US
dc.identifier.journalIEEE ACCESSen_US
dc.citation.volume7en_US
dc.citation.spage130168en_US
dc.citation.epage130179en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000487541800001en_US
dc.citation.woscount0en_US
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