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dc.contributor.authorYu, Chang-Hungen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2019-12-13T01:12:54Z-
dc.date.available2019-12-13T01:12:54Z-
dc.date.issued2016-01-01en_US
dc.identifier.isbn978-1-4503-4185-1en_US
dc.identifier.urihttp://dx.doi.org/10.1145/2934583.2934630en_US
dc.identifier.urihttp://hdl.handle.net/11536/153320-
dc.description.abstractWe evaluate and benchmark the performance of logic circuits and stability/performance of 6T SRAM cells using monolayer and bilayer TMD devices based on ITRS 2028 (5.9nm) technology node. For the performance benchmarking of logic circuits, the tradeoff between electrostatic integrity ( monolayer favored) and carrier mobility (bilayer favored), and the issues regarding the uncertainties in the mobility ratio and source/drain series resistance, the underlap device design, and the off-current spec., etc. are comprehensively addressed. In the evaluation of SRAM cells, the cell immunity to random variations is focused. Besides, the impact of high R-SD of TMD materials on RSNM variability is also investigated. The source/drain underlap design is shown to alleviate the larger variability of bilayer SRAM cells. Finally, with superior electrostatics and immunity to random variations, the monolayer TMD devices are favored for low-power logic and SRAM applications; while the bilayer devices, with higher carrier mobility, are more suitable for high-performance logic and SRAM applications.en_US
dc.language.isoen_USen_US
dc.subjectTwo-dimensional (2D) materialsen_US
dc.subjecttransition metal dichalcogenide (TMD)en_US
dc.subjectmonolayeren_US
dc.subjectbilayeren_US
dc.subjectlow-poweren_US
dc.subjectvariabilityen_US
dc.subjectlogic circuitsen_US
dc.subject6T SRAM cellsen_US
dc.titleBenchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cellsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1145/2934583.2934630en_US
dc.identifier.journalISLPED '16: PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGNen_US
dc.citation.spage242en_US
dc.citation.epage247en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000491866200044en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper