完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yu, Chang-Hung | en_US |
dc.contributor.author | Su, Pin | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.date.accessioned | 2019-12-13T01:12:54Z | - |
dc.date.available | 2019-12-13T01:12:54Z | - |
dc.date.issued | 2016-01-01 | en_US |
dc.identifier.isbn | 978-1-4503-4185-1 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1145/2934583.2934630 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/153320 | - |
dc.description.abstract | We evaluate and benchmark the performance of logic circuits and stability/performance of 6T SRAM cells using monolayer and bilayer TMD devices based on ITRS 2028 (5.9nm) technology node. For the performance benchmarking of logic circuits, the tradeoff between electrostatic integrity ( monolayer favored) and carrier mobility (bilayer favored), and the issues regarding the uncertainties in the mobility ratio and source/drain series resistance, the underlap device design, and the off-current spec., etc. are comprehensively addressed. In the evaluation of SRAM cells, the cell immunity to random variations is focused. Besides, the impact of high R-SD of TMD materials on RSNM variability is also investigated. The source/drain underlap design is shown to alleviate the larger variability of bilayer SRAM cells. Finally, with superior electrostatics and immunity to random variations, the monolayer TMD devices are favored for low-power logic and SRAM applications; while the bilayer devices, with higher carrier mobility, are more suitable for high-performance logic and SRAM applications. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Two-dimensional (2D) materials | en_US |
dc.subject | transition metal dichalcogenide (TMD) | en_US |
dc.subject | monolayer | en_US |
dc.subject | bilayer | en_US |
dc.subject | low-power | en_US |
dc.subject | variability | en_US |
dc.subject | logic circuits | en_US |
dc.subject | 6T SRAM cells | en_US |
dc.title | Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.doi | 10.1145/2934583.2934630 | en_US |
dc.identifier.journal | ISLPED '16: PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | en_US |
dc.citation.spage | 242 | en_US |
dc.citation.epage | 247 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000491866200044 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |