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dc.contributor.authorChiang, C. K.en_US
dc.contributor.authorHusan, P.en_US
dc.contributor.authorLou, Y. C.en_US
dc.contributor.authorLi, F. L.en_US
dc.contributor.authorHsieh, E. R.en_US
dc.contributor.authorLiu, C. H.en_US
dc.contributor.authorChung, Steve S.en_US
dc.date.accessioned2020-01-02T00:03:27Z-
dc.date.available2020-01-02T00:03:27Z-
dc.date.issued2019-01-01en_US
dc.identifier.issn2161-4636en_US
dc.identifier.urihttp://hdl.handle.net/11536/153322-
dc.description.abstractWe develop experimental approaches to quantitatively extract the negative capacitance of MIM in a gate stacked NCFET. It was found that the NC effect is highly dependent on the grain and dipole behaviors with different annealing temperature. Also, to achieve a better design of high-performance NCFET, we explore not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it adversely generated the degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable performance can be achieved.en_US
dc.language.isoen_USen_US
dc.titleThe Understanding of Gate Capacitance Matching on Achieving a High Performance NC MOSFET with Sufficient Mobilityen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 SILICON NANOELECTRONICS WORKSHOP (SNW)en_US
dc.citation.spage103en_US
dc.citation.epage104en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000501001400050en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper