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dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorKuan, Chin-Ien_US
dc.date.accessioned2020-01-02T00:03:29Z-
dc.date.available2020-01-02T00:03:29Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-1853-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/153336-
dc.description.abstractImpact of source/drain contacts on the operation performance of three-dimensional (3-D) zinc-oxide (ZnO) logic inverters is explored in this work. The 3-D inverters consisting of a load vertically stacking on a driver were constructed with the film-profile-engineered (FPE) approach. Use of an ultrathin ZnON contact layer is proposed and demonstrated to be effective in reducing the source/drain (S/D) series resistances (RSD) of the devices. From the material characterization, the improvement in the electrical characteristics is attributed to the suppression of an insulating interfacial oxide layer present at the contact interface which may impede the carrier transport. Measurement results of inverters indicate that the voltage gain can be improved from 9.7 V/V to 13.2 V/V as the scheme is implemented.en_US
dc.language.isoen_USen_US
dc.subjectFilm profile engineering (FPE)en_US
dc.subjectoxide semiconductoren_US
dc.subjectzinc-oxide (ZnO)en_US
dc.subjectzinc oxynitride (ZnON)en_US
dc.subjectinverteren_US
dc.subjectthin-film transistors (TFTs)en_US
dc.subjectvoltage gainen_US
dc.titleA Novel Three-Dimensional Submicron ZnO Inverter Technology with Refined Contact Designen_US
dc.typeProceedings Paperen_US
dc.identifier.journal17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000502601900037en_US
dc.citation.woscount0en_US
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