Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Huang, Yu-An | en_US |
dc.contributor.author | Yeh, Yu-Hsiang | en_US |
dc.contributor.author | Lin, Horng-Chih | en_US |
dc.contributor.author | Li, Pei-Wen | en_US |
dc.date.accessioned | 2020-01-02T00:03:29Z | - |
dc.date.available | 2020-01-02T00:03:29Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.issn | 2161-4636 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/153342 | - |
dc.description.abstract | We employed Sentaurus TCAD simulation to explore the impacts of major structural parameters on the electrical characteristics of poly-Si TFTs with T-gate and air spacers. The effects and trade-off between the source/drain (S/D) junctions relative to T-gate are discussed with the aim to find insightful information for the design and fabrication of real devices. Influences of the gate geometry on the parasitic capacitances of the T-gate devices are also simulated. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Structual Design of T-gate, Air-spacer Poly-Si TFTs for RF applications | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 SILICON NANOELECTRONICS WORKSHOP (SNW) | en_US |
dc.citation.spage | 35 | en_US |
dc.citation.epage | 36 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000501001400017 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |