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dc.contributor.authorLiu, Yu-Hengen_US
dc.contributor.authorZhan, Ting-Chienen_US
dc.contributor.authorWang, Tahuien_US
dc.contributor.authorTsai, Wen-Jeren_US
dc.contributor.authorLu, Tao-Chengen_US
dc.contributor.authorChen, Kuang-Chaoen_US
dc.contributor.authorLu, Chih-Yuanen_US
dc.date.accessioned2020-01-02T00:04:18Z-
dc.date.available2020-01-02T00:04:18Z-
dc.date.issued2019-12-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2019.2949251en_US
dc.identifier.urihttp://hdl.handle.net/11536/153361-
dc.description.abstractWe investigate electron and hole lateral migration in retention loss in a multilevel charge trap flash memory. We use hot electron program and band-to-band tunneling hot hole erase to inject various amounts of electrons and holes at the two ends of a SONOS cell. A random telegraph signal (RTS) method is used to distinguish electron and hole lateral movements in silicon nitride. In retention measurement, we apply a voltage to the gate or the source/drain to enhance or retard trapped charge vertical loss and lateral migration. From the evolution characteristics of RTS and traces in retention, we are able to identify the separate roles of electron vertical loss, electron lateral migration, and hole lateral migration in different data patterns. Due to the interaction of stored electrons and holes, we find that retention loss in a program state exhibits a turnaround characteristic as program level increases. loss at low program levels is attributed to hole lateral migration from a neighboring bit. At higher program levels, the influence of hole lateral migration is reduced and loss is dominated by electron vertical loss and lateral migration.en_US
dc.language.isoen_USen_US
dc.subjectData patternen_US
dc.subjectelectron and hole lateral migrationen_US
dc.subjectmultilevel flash memoryen_US
dc.subjectrandom telegraph signal (RTS)en_US
dc.titleInvestigation of Electron and Hole Lateral Migration in Silicon Nitride and Data Pattern Effects on ${V}_{{t}}$ Retention Loss in a Multilevel Charge Trap Flash Memoryen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2019.2949251en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume66en_US
dc.citation.issue12en_US
dc.citation.spage5155en_US
dc.citation.epage5161en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000502043000016en_US
dc.citation.woscount0en_US
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