標題: Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology
作者: Chung, Yun-Yan
Lu, Kuan-Cheng
Cheng, Chao-Ching
Li, Ming-Yang
Lin, Chao-Ting
Li, Chi-Feng
Chen, Jyun-Hong
Lai, Tung-Yen
Li, Kai-Shin
Shieh, Jia-Min
Su, Sheng-Kai
Chiang, Hung-Li
Chen, Tzu-Chiang
Li, Lain-Jong
Wong, H-S Philip
Jian, Wen-Bin
Chien, Chao-Hsin
電子物理學系
電子工程學系及電子研究所
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
關鍵字: Area selective chemical reaction deposition (CVD);p-MOSFET;short channel device;tungsten disulfide;WS2
公開日期: 1-Dec-2019
摘要: For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10(6), a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
URI: http://dx.doi.org/10.1109/TED.2019.2946101
http://hdl.handle.net/11536/153362
ISSN: 0018-9383
DOI: 10.1109/TED.2019.2946101
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 66
Issue: 12
起始頁: 5381
結束頁: 5386
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