Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs

標題:	Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
作者:	Su, Pin You, Wei-Xiang 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	1-一月-2019
URI:	http://hdl.handle.net/11536/153670
ISBN:	978-1-7281-0942-8
ISSN:	1930-8868
期刊:	2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)
起始頁:	0
結束頁:	0
顯示於類別：	會議論文