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dc.contributor.authorChang, Li-Pinen_US
dc.contributor.authorCheng, Chia-Hsiangen_US
dc.contributor.authorChang, Shu-Tingen_US
dc.contributor.authorChou, Po-Hanen_US
dc.date.accessioned2020-03-02T03:23:33Z-
dc.date.available2020-03-02T03:23:33Z-
dc.date.issued2020-02-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2018.2887046en_US
dc.identifier.urihttp://hdl.handle.net/11536/153811-
dc.description.abstractSolid state disks (SSDs) employ internal parallelism to boost their input/output (I/O) performance, but a high degree of flash parallelism inevitably consumes a high level of current. To budget power or support multiple power sources, system software may force an SSD into a new power mode that has a specific current supply limit. This paper introduces a firmware approach to optimize SSD internal parallelism subject to a current supply limit. The proposed method involves two steps. First, we constructed current models of flash operations on the basis of real-world measurement results. Second, we designed a firmware scheduler to determine the actual starting time of each flash operation. The proposed scheduler accounted for flash aging, process variation, and internal resource contention, and it avoided any current cap violation by checking a few time points instead of every unit of time. Our experimental results indicated that the proposed approach outperformed existing methods with respect to I/O response time and throughput under realistic workloads.en_US
dc.language.isoen_USen_US
dc.subjectCurrent measurementen_US
dc.subjectParallel processingen_US
dc.subjectSDRAMen_US
dc.subjectCurrent suppliesen_US
dc.subjectThroughputen_US
dc.subjectAgingen_US
dc.subjectTime factorsen_US
dc.subjectFlash memory managementen_US
dc.subjectpower managementen_US
dc.subjectsolid state disks (SSDs)en_US
dc.titleCurrent-Aware Flash Scheduling for Current Capping in Solid State Disksen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2018.2887046en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume39en_US
dc.citation.issue2en_US
dc.citation.spage321en_US
dc.citation.epage334en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000510773200004en_US
dc.citation.woscount0en_US
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