Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines

Abstract

In order to improve design productivity, proper layout automation tools are desired for analog circuits. Layout migration is one possible approach to generate a new layout for given circuits with different device sizes or different technology, and still keep the original layout topology. However, routing behaviors are often not mentioned in previous works, which requires a complete rerouting that may not follow the original style. Pan [16] first proposed a Constrained Delaunay Triangulation (CDT) based model to keep the routing behavior during layout migration. However, because the device sizes and related distance may be different in the new layout, some reference lines in CDT models may be removed, resulting in some missing nets after migration. In this paper, a novel Cartesian Detection Line (CDL) based model is proposed to preserve the routing behavior in original layouts. Because alternative lines in the modified placement can be easily found to prevent from missing nets, the proposed CDL model greatly improves the routing completeness during layout migration. Several routing refinement techniques are also proposed to solve the routing issues due to block displacement. In our experiments, the routing completeness can be improved to almost 100% with the proposed CDL model, which greatly reduces the design efforts.