標題: Effects of a dual spacer on electrical characteristics and random telegraph noise of gate-all-around silicon nanowire p-type metal-oxide-semiconductor field-effect transistors
作者: Kola, Sekhar Reddy
Li, Yiming
Thoti, Narasimhulu
交大名義發表
電機工程學系
電信工程研究所
電機資訊國際碩士學位學程
National Chiao Tung University
Department of Electrical and Computer Engineering
Institute of Communications Engineering
EECS International Graduate Program-Master
公開日期: 1-Apr-2020
摘要: Using a dual spacer consisting of 50% SiO2 and 50% HfO2, the ratio of the on-state current/the off-state current in the order of 10(6) is achieved for the explored devices. Based on the experimentally validated simulation, the result indicates that the variation of gate-capacitance is significant owing to the sizeable parasitic capacitance resulting from the spacer. The role of the spacer acts as the parallel plate capacitor, the amount of gate capacitance will be increased largely with the HfO2 due to its high parasitic capacitance. For the devices without any spacers, induced by a donor-type single charge trap (SCT), the statistically calculated highest amplitude of random telegraph noise (RTN) is 2.32%. It occurs when the SCT locates in the middle of the channel due to the high occurrence of capture and emission for SCT under low gate voltage. Notably, for devices with considerable spacers, the RTN can be significantly suppressed (<= 1%). (C) 2020 The Japan Society of Applied Physics
URI: http://dx.doi.org/10.7567/1347-4065/ab5b7c
http://hdl.handle.net/11536/154173
ISSN: 0021-4922
DOI: 10.7567/1347-4065/ab5b7c
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS
Volume: 59
起始頁: 0
結束頁: 0
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