Study on random telegraph noise of high-idmetal-gate gate-all-around poly-Si nanowire transistors

Abstract

In this Paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-kappa oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side. (C) 2020 The Japan Society of Applied Physics