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dc.contributor.authorJiang, Jheng-Yien_US
dc.contributor.authorHung, Jia-Qingen_US
dc.contributor.authorHuang, Pin-Weien_US
dc.contributor.authorWu, Tian-Lien_US
dc.contributor.authorHuang, Chi-Fangen_US
dc.date.accessioned2020-05-05T00:02:22Z-
dc.date.available2020-05-05T00:02:22Z-
dc.date.issued2020-04-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.7567/1347-4065/ab656den_US
dc.identifier.urihttp://hdl.handle.net/11536/154176-
dc.description.abstractIn this study, Si implantation was used to improve the interface properties of SiC/SiO2 in 4H-SiC lateral MOSFETs. In lateral n-channel MOSFETs, a 4%-6% improvement on the linear and saturation current was observed with Si implantation, From high/low-frequency CV measurements, the Si implanted n-type MOS capacitor showed a 20% lower interface state density than the non-implanted ones at an energy level of E-C - E = 0.2 eV, without degrading oxide integrity. Lateral p-channel MOSFETs, on the other hand, showed a 36.5% reduction in the linear current and a 16.6% reduction in the saturation current with Si implantation. Furthermore, the temperature coefficients of lateral and vertical MOSFETs implanted, by Si ere monitored up to 175 degrees C. The temperature coefficients of the Si-implanted n-channel and p-channel lateral MOSFETs were nearly identical to those of their non-implanted counterparts. (C) 2020 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleStudy on the effects of Si implantation on the interface of 4H-SiC lateral MOSFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.7567/1347-4065/ab656den_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume59en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000519630000041en_US
dc.citation.woscount0en_US
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